SEGGER J-Link Pro: an exhaustive review

SEGGER J-Link PRO an exhaustive review

1 Meeting J-Link

In our minds, we have always seen SEGGER debugging solutions like a professional but costly tools: a debugger to perform advanced operations but definitely too much for a student. Some time ago we heard about a new version of SEGGER, the J-Link EDU, which is cheaper and addressed virtually to us. It started to take shape the idea of using it as external debugger for these ARM evaluation kit which comes without a debugger.

Some month ago SEGGER proposed a firmware suitable for STM32 Nucleo on-chip debugger which makes J-Link available also for the STM32 ecosystem and they notified us this solution commenting our STM32 Nucleo-144 review. After an exchange of reciprocal opinion they have definitely caught our attention and we have decided to ask them for a J-Link PRO in order to test it. continue reading…

Sampling and dimming (ADC and PWM)

Sampling and Dimming

1 Sampling using ADC

Potentiometer operation principle
Fig.1 – Potentiometer operation principle.

An Analog to digital converter is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity’s amplitude.

In this demo, we are sampling voltage across a potentiometer to establish its position. A potentiometer is a three-pin knob that provides a variable resistance between W-A and W-B pins (Fig.1). Amount of resistance between A and B is constant, but by turning the shaft of the potentiometer, we change the amount of resistance on either side of W.

Connecting A to 3 V, B to GND (or vice versa) and sampling voltage between W and GND we could measure wiper position: according to voltage divider, sampled voltage would be proportional to amount of resistance between W and pin connected to GND.

2 ADC in ChibiOS

STM32 has more than an ADC. As always, we had to enable ADC subsystem in halconf.h and proper driver in mcuconf.h.

Every ADC has more than a channel. We could sample from these channels choosing a custom sequence. In order to do that we had to configure some ADC register though ADCConversionGroup. Moreover, we could configure sampling frequency and mode. Our conversion group is:

We are sampling in a not circular way, from a single channel (ADC_CHANNEL_IN0). Sampling frequency is equal to three main clock cycle (ADC_SAMPLE_3), (For more information look for ADC registers on Reference Manual).

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Meeting SPI

Meeting SPI

1 The Serial Peripheral Interface

1.1 Introducing SPI

Communicating by a serial bus instead of a parallel one could be very useful when we need to send out a big number of words or fixing a constraint on wires. The Serial Peripheral Interface bus, also known as SPI bus, is a synchronous, serial communication peripheral which communicates in full duplex mode using a master-slave architecture with a single master.
That means we have always a single master and one or more slaves. The communications is bi-directional (i.e. data flows from master to slave but also from slave to master). Since this bus is synchronous, the master (that handles and manages the communication) provides also a clock on a specific line (known as SCK or CLK) so the data is send-out/captured on a clock edge.

Both master and slave send-out and capture 1 bit per clock period. Using other words for each clock period master send and receive a bit and the same happens for slave: to do this are required two separated line (MISO and MOSI).

As there may be more than a slave, the master needs for a slave selector and this is implemented using an additional line for each slave. In this way only the slave having its select line lowered actually communicates with master. Because of that this line is know as Slave Select (SS) as well as Chip Select (CS) (or also as nCS, nSS where n means negate). Nothing has been said on data size as it depends on hardware. However, most common word sizes are 8-bit, 12-bit or 16-bit.

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